Layout technique for middle-end-of-line

ABSTRACT

In certain aspects of the disclosure, a die includes one or more fins, a gate formed over a first portion of the one or more fins, and a first source/drain contact formed over a second portion of the one or more fins, wherein the first source/drain contact includes an extended portion that does not overlap the one or more fins. The die also includes first and second metal lines formed from a first metal layer, wherein the first and second metal lines are spaced apart. The die further includes a first via connecting the first source/drain contact to the first metal line, and a second via connecting the first source/drain contact to the second metal line, wherein the second via lies within the extended portion of the first source/drain contact.

RELATED APPLICATION BACKGROUND Field

Aspects of the present disclosure relate generally to chip layout, andmore particularly, to chip layout techniques for reducingmiddle-end-on-line (MEOL) parasitic resistance.

Background

The geometries of structures on semiconductor dies continue to scaledown with advances in chip fabrication. Metal routing in themiddle-end-of-line (MEOL) has become increasing more complex asgeometries have scaled down and additional metal routing structures havebeen added in advanced deep sub-micron fabrication processes.

SUMMARY

The following presents a simplified summary of one or more embodimentsin order to provide a basic understanding of such embodiments. Thissummary is not an extensive overview of all contemplated embodiments,and is intended to neither identify key or critical elements of allembodiments nor delineate the scope of any or all embodiments. Its solepurpose is to present some concepts of one or more embodiments in asimplified form as a prelude to the more detailed description that ispresented later.

A first aspect relates to a die. The die includes one or more fins, agate formed over a first portion of the one or more fins, and a firstsource/drain contact formed over a second portion of the one or morefins, wherein the first source/drain contact includes an extendedportion that does not overlap the one or more fins. The die alsoincludes first and second metal lines formed from a first metal layer,wherein the first and second metal lines are spaced apart. The diefurther includes a first via connecting the first source/drain contactto the first metal line, and a second via connecting the firstsource/drain contact to the second metal line, wherein the second vialies within the extended portion of the first source/drain contact.

A second aspect relates to a die. The die includes one or more fins, afirst gate formed over a first portion of the one or more fins, and afirst source/drain contact formed over a second portion of the one ormore fins, wherein the first source/drain contact includes an extendedportion that does not overlap the one or more fins. The die alsoincludes a second source/drain contact formed over a third portion ofthe one or more fins, a second gate formed over a fourth portion of theone or more fins, wherein the second source/drain contact is between thefirst gate and the second gate, and a third source/drain contact formedover a fifth portion of the one or more fins, wherein the thirdsource/drain contact includes an extended portion that does not overlapthe one or more fins. The die also includes first and second metal linesformed from a first metal layer, wherein the first and second metallines are spaced apart, a first via connecting the first source/draincontact to the first metal line, a second via connecting the firstsource/drain contact to the second metal line, wherein the second vialies within the extended portion of the first source/drain contact, athird via connecting the third source/drain contact to the first metalline, and a fourth via connecting the third source/drain contact to thesecond metal line, wherein the fourth via lies within the extendedportion of the third source/drain contact.

To the accomplishment of the foregoing and related ends, the one or moreembodiments include the features hereinafter fully described andparticularly pointed out in the claims. The following description andthe annexed drawings set forth in detail certain illustrative aspects ofthe one or more embodiments. These aspects are indicative, however, of afew of the various ways in which the principles of various embodimentsmay be employed and the described embodiments are intended to includeall such aspects and their equivalents.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A shows a perspective view of a structure including a FinFET andinterface structures for the FinFET according to certain aspects of thepresent disclosure.

FIG. 1B shows a perspective view of the structure in FIG. 1A in whichsome of the interface structures shown in FIG. 1A are not shown in FIG.1B in order to provide an unobstructed view of certain features of thestructure.

FIG. 1C shows a top view of the FinFET shown in FIGS. 1A and 1Baccording to certain aspects of the present disclosure.

FIG. 2A shows a perspective view of a structure including a FinFET andinterface structures for the FinFET with reduced parasitic resistanceaccording to certain aspects of the present disclosure.

FIG. 2B shows a perspective view of the structure in FIG. 2A in whichsome of the interface structures shown in FIG. 2A are not shown in FIG.2B in order to provide an unobstructed view of certain features of thestructure.

FIG. 2C shows a top view of the FinFET shown in FIGS. 2A and 2Baccording to certain aspects of the present disclosure.

FIG. 2D shows an example in which portions of the fins in the FinFET aremerged according to certain aspects of the present disclosure.

FIG. 2E shows an example of sidewall spacers used to define theboundaries of the merged portions of the fins according to certainaspects of the present disclosure.

FIG. 3A shows a top view of a multi-finger transistor according tocertain aspects of the present disclosure.

FIG. 3B shows a top view of interface structures with reduced parasiticresistance for the multi-finger transistor according to certain aspectsof the present disclosure.

FIG. 3C shows a perspective view of the interface structures and themulti-finger transistor shown in FIG. 3B.

FIG. 3D shows a top view of the interface structures from a metal-0 (MO)layer to a metal-1 (M1) layer according to certain aspects of thepresent disclosure.

FIG. 4 shows a circuit model of the multi-finger transistor according tocertain aspects of the present disclosure.

DETAILED DESCRIPTION

The detailed description set forth below, in connection with theappended drawings, is intended as a description of variousconfigurations and is not intended to represent the only configurationsin which the concepts described herein may be practiced. The detaileddescription includes specific details for the purpose of providing athorough understanding of the various concepts. However, it will beapparent to those skilled in the art that these concepts may bepracticed without these specific details. In some instances, well-knownstructures and components are shown in block diagram form in order toavoid obscuring such concepts.

FIGS. 1A-1C show an exemplary structure 100 formed above the substrateof a semiconductor die according to certain aspects of the presentdisclosure. The structure 100 includes a transistor and interfacestructures for interconnecting the transistor with another transistor(e.g., within the same cell) and/or connecting the transistor to uppermetal layers in the back-end-of-line (BEOL) of the die. Although onlyone transistor is shown in FIGS. 1A-1C, it is to be appreciated that adie typically includes millions to billions of transistors.

In this example, the transistor is a Fin Field Effect Transistor(FinFET) having a three-dimensional structure. The FinFET includes oneor more fins 110-1 to 110-4 that run parallel to each other, and extendin the lateral direction indicated by doubled-arrow line 112 in FIGS.1A-1C. As used herein, the term “lateral” refers to a direction that ishorizontal with respect to the substrate of the die. The fins 110-1 to110-4 may be made of silicon, silicon germanium, silicon carbon, etc.Although four fins 110-1 to 110-4 are shown in the example in FIGS.1A-1C, it is to be understood that the FinFET may include a differentnumber of fins (e.g., one fin, two fins, three fins, etc.). Further,although the fins 110-1 to 110-4 are depicted in FIGS. 1A-1C as havingrectangular cross sections (profiles), it is to be understood that thefins may having other cross-sectional shapes. For example, each fin mayhave a tapered cross section, in which the fin is thicker at the basethan the top.

The FinFET also includes a gate 120 that runs perpendicular to the fins110-1 to 110-4, and extends in the lateral direction indicated bydoubled-arrow line 122 in FIGS. 1A-1C, which is perpendicular to lateraldirection 112. The gate 120 is formed over a middle portion of the fins110-1 to 110-4 such that first and second side portions of the fins110-1 to 110-4 extend from opposite sides of the gate 120. This is shownin FIG. 1C, which shows a top view of the FinFET. The middle portion ofthe fins form the channel of the FinFET, in which a voltage applied tothe gate 120 controls the conductance of the channel. The gate 120 maywrap around three or more sides of each fin (e.g., the top side and twoopposite sidewalls of each fin). This increases the surface area betweenthe gate 120 and the fins 110-1 to 110-4, providing improved electricalcontrol over the channel conductance of the FinFET. The side portions ofthe fins 110-1 to 110-4 extending from the opposite sides of the gate120 form the source and drain of the FinFET, as discussed further below.

The FinFET may also include a thin dielectric layer (not shown)interposed between the fins 110-1 to 110-4 and the gate 120. Thedielectric layer may include a hafnium-based oxide dielectric, oranother dielectric material.

The structure 100 also includes a first source/drain contact 115 and asecond source/drain contact 125 on opposite sides of the gate 120 (referto FIG. 1C). As used herein, the term “source/drain” means that acontact provides electrical contact with either the source or the drainof the FinFET. For example, the first source/drain contact 115 mayprovide contact with the drain of the FinFET, and the secondsource/drain contact 125 may provide contact with the source of theFinFET, or vice versa.

The first source/drain contact 115 is formed over the first side portionof the fins 110-1 to 110-4, and acts as a source or drain contact of theFinFET. The first source/drain contact 115 may contact one or more sidesof each fin (e.g., the top side and two opposite sidewalls of each fin).The first source/drain contact 115 is made of one or more conductivematerials (e.g., copper and/or another metal). The structure 100 mayalso include a sidewall spacer (not shown) between the gate 120 and thefirst source/drain contact 115. The sidewall spacer may be used tofacilitate self alignment of the contact 115 and/or gate 120 duringfabrication and prevent a short between the gate 120 and the contact115.

The second source/drain contact 125 is formed over the second sideportion of the fins 110-1 to 110-4, and acts as a source or draincontact of the FinFET. As shown in FIGS. 1A-1C, the second source/draincontact 125 is located on the opposite side of the gate 120 as the firstsource/drain contact 115. The second source/drain contact 125 maycontact one or more sides of each fin (e.g., the top side and twoopposite sidewalls of each fin). The second source/drain contact 125 ismade of one or more conductive materials (e.g., copper or anothermetal). The structure 100 may include a sidewall spacer (not shown)between the gate 120 and the second source/drain contact 125. Thesidewall spacer may be used to facilitate self alignment of the contact125 and/or gate 120 during fabrication and prevent a short between thegate 120 and the contact 125.

The structure 100 also includes a gate contact 130 formed on top of thegate 120. The gate contact 130 is made of one or more conductivematerials (e.g., copper and/or another metal).

FIG. 1C shows a top view of the FinFET, the first source/drain contact115, the second source/drain contact 125, and the gate contact 130. Asshown in FIG. 1C, the fins 110-1 to 110-4 extend laterally from oppositesides of the gate 120. The gate 130 is formed over the middle portion ofthe fins, the first source/drain contact 115 is formed over the firstside portion of the fins, and the second source/drain contact 125 isformed over the second side portion of the fins.

Referring to FIG. 1A, the structure 100 includes an interface structurefor the first source/drain contact 115. The interface structure includesa first metal-0 (M0) line 135 above the first source/drain contact 115,and a first metal-1 (M1) line 140 above the first M0 line 135. The firstM0 line 135 is formed from a metal-0 (M0) layer of the die, and thefirst M1 line 140 is formed from a metal-1 (M1) layer of the die that isabove the M0 layer. The M0 layer and the M1 layer may be used to formmetal lines for interconnecting transistors (e.g., within the same cell)and connecting transistors to upper metal layers of the die (i.e., metallayers above metal layer M1). Metal lines may be formed from the M0 andM1 layers using lithography and etching and/or other fabricationtechniques known in the art.

The interface structure also includes via 132 between the firstsource/drain contact 115 and the first M0 line 135, and via 138 betweenthe first M0 line 135 and the first M1 line 140. In this example, via132 is a vertical interconnect structure connecting the firstsource/drain contact 115 to the first M0 line 135, and via 138 is avertical interconnect structure connecting the first M0 line 135 to thefirst M1 line 140. As used herein, the term “vertical” refers to adirection that is perpendicular to the substrate of the die. In FIGS.1A-1C, a via between a source/drain contact and an M0 line is labeled“VD”, and a via between an M0 line and an M1 line is labeled “V0.” Inthe discussion below, a via between a source/drain contact and an M0line is referred to as a “VD via”, and a via between an M0 line and anM1 line is referred to as a “V0 via.”

As shown in FIG. 1A, the first M0 line 135 and the first M1 line 140 areperpendicular to each other. As discussed above, the first M0 line 135is formed from the M0 layer of the die. The M0 layer is found inadvanced deep sub-micron processes (nodes). In these processes, the M0layer is typically used to form unidirectional metal lines running inone lateral direction, and the M1 layer is used to form unidirectionalmetal lines running in a lateral direction that is perpendicular to thelater direction of the M0 metal lines. The use of unidirectional metallines allows advanced processes to achieve higher resolution at theexpense of requiring an additional metal layer (i.e., M0 layer) forbi-directional metal routing.

The structure 100 includes an interface structure for the gate contact130. The interface structure for the gate contact 130 includes a secondM0 line 145 above the gate contact 130, and a second M1 line 150 abovethe second M0 line 145. The second M0 line 145 is formed from the M0layer of the die, and the second M1 line 150 is formed from the M1 layerof the die. The interface structure also includes via 142 between thegate contact 130 and the second M0 line 145, and V0 via 148 between thesecond M0 line 145 and the second M1 line 150. In this example, via 142is a vertical interconnect structure connecting the gate contact 130 tothe second M0 line 145, and via 148 is a vertical interconnect structureconnecting the second M0 line 145 to the second M1 line 150. In FIGS.1A-1C, a via between a gate contact and an M0 line is labeled “VG.” Inthe discussion below, a via between a gate contact and an M0 line isreferred to as a “VG via.”

As shown in FIG. 1A, the second M0 line 145 and the second M1 line 150are perpendicular to each other. Also, the second M0 line 145 runsparallel to the first M0 line 135, and the second M1 line 150 runsparallel to the first M1 line 140.

Referring to FIG. 1B, the structure 100 also includes an interfacestructure for the second source/drain contact 125. Note that theinterface structures for the gate contact 130 and the first source/draincontact 115 are not shown in FIG. 1B in order to provide an unobstructedview of the interface structure for the second source/drain contact 125.

The interface structure includes a third M0 line 155 above the secondsource/drain contact 125, and a third M1 line 160 above the third M0line 155. The third M0 line 155 is formed from the M0 layer of the die,and the third M1 line 160 is formed from the M1 layer of the die. Theinterface structure also includes VD via 152 between the secondsource/drain contact 125 and the third M0 line 155, and V0 via 158between the third M0 line 155 and the third M1 line 160. In thisexample, VD via 152 is a vertical interconnect structure connecting thesecond source/drain contact 125 to the third M0 line 155, and V0 via 158is a vertical interconnect structure connecting the third M0 line 155 tothe third M1 line 160. As shown in FIG. 1B, the third M0 line 155 andthe third M1 line 160 are perpendicular to each other.

Referring back to FIG. 1A, the first, second and third M0 lines 135, 145and 155 run parallel to each other, and the first, second and third M1lines 140, 150 and 160 run parallel to each other. The first M0 line 135and the third M0 line 155 are spaced apart by a spacing (labeled“spacing” in FIG. 1A) in lateral direction 122. The spacing between theM0 lines 135 and 155 typically cannot be smaller than a minimum linespacing for the M0 line specified by a chip layout design rule.

Thus, the interface structures for the FinFET include M0 lines, M1lines, VD vias, V0 vias and one or more VG vias. The addition of M0lines and V0 vias in the interface structures and the finer geometriesin advanced deep submicron processes result in increased parasiticseries resistance. The increased parasitic resistance increases IR dropsin the interface structures, which reduce the voltage headroom of thetransistor, and therefore negatively impact performance. The increasedparasitic resistance makes the design of ubiquitous circuit topologies,such as low-impedance I/O drivers, especially challenging. The parasiticresistance is only expected to get worse as dimensions scale down.

The parasitic resistance can be reduced by increasing the number ofvias. However, the high metal routing density in the interfacestructures and chip layout design rule restrictions make it verydifficult to accommodate additional vias to reduce parasitic resistance.For example, an additional VD via cannot be placed on the area of thefirst source/drain contact 115 referenced by reference number 170 inFIG. 1A. This is because the additional VD would require an M0 lineabove the area 170 of the first source/drain contact 115, which wouldinterfere with the third M0 line 155 used for the second source/draincontact 125. For this reason, the VD via 132 of the first source/draincontact 115 and the VD via 152 of the second source/drain contact 125are offset from each other in lateral direction 122, as shown in FIG.1A.

Embodiments of the present disclosure extend the length of a contact(e.g., source/drain contact) beyond an active region of a transistor inorder to increase the area of the contact. The increased area allows oneor more additional vias (e.g., one or more VD vias) to be placed on thecontact without violating the chip layout design rules. The one or moreadditional vias reduce parasitic resistance in the interface structureof the contact, thereby improving performance.

In this regard, FIG. 2A-2C show a structure 200 according to certainaspects of the present disclosure. The structure 200 includes a FinFETand interface structures for interconnecting the FinFET with anothertransistor (e.g., within the same cell) and/or connecting the FinFET toupper metal layers in the back-end-of-line (BEOL) of the die.

The FinFET includes one or more fins 210-1 to 210-4, which extend in thelateral direction 112. The fins 210-1 to 210-4 may be the same as thefins 110-1 to 110-4 shown in FIGS. 1A-1C. The FinFET also includes agate 220 formed over the middle portion of the fins 210-1 to 210-4 suchthat first and second side portions of the fins 210-1 to 210-4 extendfrom opposite sides of the gate 220. The gate 220 is similar to the gate120 in FIGS. 1A-1C except that the length of the gate 220 is increasedin the lateral direction 122, as discussed further below. The gate 220may wrap around three or more sides of each fin (e.g., the top side andtwo opposite sides of each fin). The side portions of the fins 210-1 to210-4 extending from the opposite sides of the gate 220 form the sourceand drain of the FinFET.

The FinFET may also include a thin dielectric layer (not shown)interposed between the fins 210-1 to 210-4 and the gate 220. Thedielectric layer may include a hafnium-based oxide dielectric, oranother dielectric material.

The structure 200 also includes a first source/drain contact 215 and asecond source/drain contact 225 on opposite sides of the gate 220. Thefirst source/drain contact 215 is similar to the first source/draincontact 115 in FIGS. 1A-1C except that the length of the firstsource/drain contact 215 is increased in lateral direction 122 toaccommodate an additional VD via for reduced parasitic resistance, asdiscussed further below.

The first source/drain contact 215 is formed over the first side portionof the fins 210-1 to 210-4, and acts as a source or drain contact of theFinFET. The first source/drain contact 215 may contact one or more sidesof each fin (e.g., the top side and two opposite sidewalls of each fin).The first source/drain contact 215 is made of one or more conductivematerials (e.g., copper and/or another metal). The structure 200 mayalso include a sidewall spacer (not shown) between the gate 220 and thefirst source/drain contact 215.

The second source/drain contact 225 is similar to the secondsource/drain contact 125 in FIGS. 1A-1C except that the length of thesecond source/drain contact 225 is increased in lateral direction 122 toaccommodate an additional VD via for reduced parasitic resistance, asdiscussed further below.

As shown in FIGS. 2A-2C, the second source/drain contact 225 is locatedon the opposite side of the gate 220 as the first source/drain contact215. The second source/drain contact 225 is formed over the second sideportion of the fins 210-1 to 210-4, and acts as a source or draincontact of the FinFET. The second source/drain contact 225 may contactone or more sides of each fin (i.e., the top side and two oppositesidewalls of each fin). The second source/drain contact is made of oneor more conductive materials (e.g., copper or another metal). Thestructure 200 may include a sidewall spacer (not shown) between the gate220 and the second source/drain contact 225.

The structure 200 also includes a gate contact 230 formed on top of thegate 220. The gate contact 230 is made of one or more conductivematerials (e.g., copper and/or another metal).

FIG. 2C shows a top view of the FinFET, the first source/drain contact215, the second source/drain contact 225, and the gate contact 230. Asshown in FIG. 2C, the fins 210-1 to 210-4 extend laterally from oppositesides of the gate 220. The gate 230 is formed over the middle portion ofthe fins, the first source/drain contact 215 is formed over the firstside portion of the fins, and the second source/drain contact 225 isformed over the second side portion of the fins.

As shown in FIGS. 2A-2C, the first source/drain contact 215 includes afirst extended portion 214 that extends beyond one edge of an activeregion 212 of the FinFET. In this example, the active region 212 spansthe fins 210-1 to 210-4 in lateral direction 122 and lateral direction112. The first source/drain contact 215 also includes a second extendedportion 216 that extends beyond an edge of the active region 212 that isopposite the edge from which the first extended portion 214 extends. Theextended portions 214 and 216 of the first source/drain contact 215 donot overlap the fins 210-1 to 210-4. Although the first source/draincontact 215 includes two extended portions in this example, it is to beunderstood that the first source/drain contact may include only one ofthe extended portions. As discussed above, the first extended portion214 increases the area of the first source/drain contact 215, allowingan additional VD via to be placed on the first source/drain contact 215for reduced parasitic resistance.

The second source/drain contact 225 includes a first extended portion224 that extends beyond one edge of the active region 212 of the FinFET,and a second extended portion 226 that extends beyond an edge of theactive region 212 that is opposite the edge from which the firstextended portion 224 extends (refer to FIG. 2C). The extended portions224 and 226 of the second source/drain contact 225 do not overlap thefins 210-1 to 210-4. Although the second source/drain contact 225includes two extended portions in this example, it is to be understoodthat the second source/drain contact may include only one of theextended portions. As discussed above, the first extended portion 224increases the area of the second source/drain contact 225, allowing anadditional VD via to be placed on the second source/drain contact 225for reduced parasitic resistance.

Th gate 220 in FIGS. 2A-2C is longer than the gate 120 in FIGS. 1A-1C.This is done in order to accommodate the extended portions of the firstand second source/drain contacts 215 and 225. Thus, the first and secondsource/drain contacts 215 and 225 and the gate 220 are extended inlateral direction 122 compared with the first and second source/draincontacts 115 and 125 and the gate 120 in FIGS. 1A-1C.

Referring to FIG. 2A, the structure 200 includes an interface structurefor the first source/drain contact 215. As discussed further, theinterface structure for the first source/drain contact 215 includes twoVD vias to reduce parasitic resistance.

The interface structure includes a first M0 line 235 above the firstsource/drain contact 215, and a first M1 line 240 above the first M0line 235. The first M0 line 235 is formed from the M0 layer of the die,and the first M1 line 240 is formed from the M1 layer of the die. Asshown in FIG. 2A, the length of the first M0 line 235 runs in lateraldirection 112, and the length of first M1 line 240 runs in lateraldirection 122, which is perpendicular to direction 112.

The interface structure also includes VD via 232 between the firstsource/drain contact 215 and the first M0 line 235, and V0 via 238between the first M0 line 235 and the first M1 line 240. VD via 232 is avertical interconnect structure connecting the first source/draincontact 215 to the first M0 line 235, and the V0 via 238 is a verticalinterconnect structure connecting the first M0 line 235 to the first M1line 240. In the example shown in FIG. 2A, VD via 232 and V0 via 238 liewithin the active region 212, and overlap one or more of the fins 210-1to 210-4.

The interface structure for the first source/drain contact 215 alsoincludes a second M0 line 236 above the first source/drain contact 215.The second M0 line 236 is formed from the M0 layer of the die, and runsparallel with the first M0 line 235. The interface structure alsoincludes VD via 231 between the first source/drain contact 215 and thesecond M0 line 236, and V0 via 237 between the second M0 line 236 andthe first M1 line 240. VD via 231 is a vertical interconnect structureconnecting the first source/drain contact 215 to the second M0 line 236,and the V0 via 237 is a vertical interconnect structure connecting thesecond M0 line 236 to the first M1 line 240.

In the example shown in FIG. 2A, VD via 231 and V0 via 237 lie withinthe first extended portion 214 of the first source/drain contact 215.The first extended portion 214 provides enough contact area toaccommodate VD via 231 while complying with chip layout design rules(e.g., minimum spacing between adjacent M0 lines). Thus, the interfacestructure in this example includes two VD vias (i.e., VD vias 231 and232). This substantially reduces parasitic resistance compared with theinterface structure for the first source/drain contact 115 in FIG. 1A,which only includes one VD via (i.e., VD via 132). In the example shownin FIG. 2A, VD via 231 does not overlap a fin.

Referring to FIG. 2B the structure 200 includes an interface structurefor the second source/drain contact 225. Note that the interfacestructure for the first source/drain contact 215 is not shown in FIG. 2Bin order to provide an unobstructed view of the interface structure forthe second source/drain 225. As discussed further below, the interfacestructure for the second source/drain 225 includes two VD vias to reduceparasitic resistance.

The interface structure includes a third M0 line 255 above the secondsource/drain contact 225, and a second M1 line 260 above the third M0line 255. The third M0 line 255 is formed from the M0 layer of the die,and the second M1 line 260 is formed from the M1 layer of the die. Asshown in FIG. 2B, the length of the third M0 line 255 runs in lateraldirection 112, and the length of second M1 line 260 runs in lateraldirection 122, which is perpendicular to direction 112.

The interface structure also includes VD via 252 between the secondsource/drain contact 225 and the third M0 line 255, and V0 via 258between the third M0 line 255 and the second M1 line 260. VD via 252 isa vertical interconnect structure connecting the second source/draincontact 225 to the third M0 line 255, and the V0 via 258 is a verticalinterconnect structure connecting the third M0 line 255 to the second M1line 260. In the example shown in FIG. 2B, VD via 252 and V0 via 258 liewithin the first extended portion 224 of the second source/drain contact225.

The interface structure for the second source/drain contact 225 alsoincludes a fourth M0 line 256 above the second source/drain contact 225.The fourth M0 line 256 is formed from the M0 layer of the die, and runsparallel with the third M0 line 235. The interface structure alsoincludes VD via 251 between the second source/drain contact 225 and thefourth M0 line 256, and V0 via 257 between the fourth M0 line 256 andthe second M1 line 260. VD via 251 is a vertical interconnect structureconnecting the second source/drain contact 225 to the fourth M0 line256, and the V0 via 257 is a vertical interconnect structure connectingthe fourth M0 line 256 to the second M1 line 260. VD via 251 and via 257lie within the active region 212.

As discussed above, VD via 252 and V0 via 258 lie within the firstextended portion 224 of the second source/drain contact 225. The firstextended portion 224 provides enough contact area to accommodate VD via252 while complying with chip layout design rules (e.g., minimum spacingbetween adjacent M0 lines). Thus, the interface structure in thisexample includes two VD vias (i.e., VD vias 251 and 252). Thissubstantially reduces parasitic resistance compared with the interfacestructure for the second source/drain contact 125 in FIG. 1A, which onlyincludes one VD via (i.e., VD via 152).

The structure 200 also includes an interface structure connected to thegate contact 230. The interface structure for the gate contact 230includes a fifth M0 line 245 above the gate contact 230, and a third M1line 250 above the fifth M0 line 245. The fifth M0 line 245 is formedfrom the M0 layer of the die, and the third M1 line 250 is formed fromthe M1 layer of the die. The interface structure also includes via 242between the gate contact 230 and the fifth M0 line 245, and V0 via 248between the fifth M0 line 245 and the third M1 line 250. In thisexample, via 242 is a vertical interconnect structure connecting thegate contact 230 to the fifth M0 line 245, and via 248 is a verticalinterconnect structure connecting the fifth M0 line 245 to the third M1line 250.

As shown in FIG. 2A, the first, second, third fourth and fifth M0 lines235, 236, 255, 256 and 245 run parallel to each other, and the first,second and third M1 lines 240, 260 and 250 run parallel to each other.The first, second, third, fourth and fifth M0 lines 235, 236, 255, 256and 245 are spaced apart from one another in lateral direction 122, inwhich the spacing between adjacent M0 lines is no smaller than a minimumline spacing specified by a chip layout design rule for the die.

As shown in FIG. 2A, the first extended portion 214 of the firstsource/drain contact 215 and the first extended portion 224 of thesecond source/drain contact 225 are on opposite sides of the activeregion 212 (opposite sides of the fins 210-1 to 210-4).

As shown in FIG. 2A, the VD vias 231 and 232 of the first source/draincontact 215 are offset from the VD vias 251 and 252 of the secondsource/drain contact 225 in the lateral direction 122.

It is to be appreciated that the M0 lines shown in FIGS. 2A and 2B mayextend further in lateral direction 112 than shown in FIGS. 2A and 2B.Also, it is to be appreciated that the M1 lines shown in FIGS. 2A and 2Bmay extend further in lateral direction 122 than shown in FIGS. 2A and2B. Further, it is to be appreciated that the fins 210-1 to 210-4 mayextend further in lateral direction 112 than shown in FIGS. 2A-2C.

Thus, embodiments of the present disclosure reduce parasitic resistanceby extending the lengths of the source/drain contacts 215 and 225 beyondthe active region 212. This increases the contact areas of the contact215 and 225, allowing additional VD vias to be placed on the contacts215 and 225 for reduced parasitic resistance.

The reduced resistance results in higher performance (e.g., higher gateover drive). The reduced resistance also reduces IR droops in theinterface structures for the contacts, resulting in improved voltageheadroom or regain voltage headroom. The reduced resistance also reducesthe impedance calibration range since the contact interface resistancecontributes less to total resistance.

Aspects of the present disclosure also provide improvedmanufacturability (i.e., less sensitivity to contact interfaceresistance which typically exhibits wide variation due to poorer controlof interface quality which primarily dictates contact resistance). Forexample, using multiple VD vias for a source/drain contact providesimproved manufacturability compared with using one VD via for thesource/drain contact. This is because an interface structure withmultiple VD vias may still work if one of the VD vias is defective,whereas an interface structure with only one VD via will not work if theone VD via is defective.

Aspects of the present disclosure also reduce routing congestion thatmight otherwise introduce more design rule check (DRC) issues. Forexample, extending the lengths of the contacts provides more area forrouting.

Aspects of the present disclosure have some drawbacks. For example,extending the lengths of the contacts incurs penalties in local area toaccount for the extension. Also, extending the lengths of thesource/drain contacts and the gate may increase parasitic capacitancebetween the source/drain contacts and the gate. However, these drawbacksare outweighed by the reduced series resistance and reduced sensitivityto variation in resistance provided by aspects of the presentdisclosure.

In FIG. 2C, the fins 210-1 to 210-4 are depicted as being discretestructures throughout their entire lengths in direction 112. However, itis to be appreciated that embodiments of the present disclosure are notlimited to this example. For instance, FIG. 2D shows an example in whichthe fins are merged on opposite sides of the gate 230 to form first andsecond merged portions 280 and 290. In this example, the firstsource/drain contact 215 (not shown in FIG. 2D) may be formed over thefirst merged portion 280, and the second source/drain contact 225 (notshown in FIG. 2D) may be formed over the second merged portion 290. Themerged portions 280 and 290 may be formed using an epitaxial growthprocess in which silicon or another material is grown on the fins tomerge the fins. The epitaxial growth may use the same material as thefins or a different material. As shown in FIG. 2D, the merged portions280 and 290 lie within the active region 212. The fins are separate(i.e., not merged) under the gate 220.

The merged portions 280 and 290 may be defined at least partially usingsidewall spacers. In this regard, FIG. 2E shows examples of sidewallspacers 291-294 that may be used to at least partially define the mergedportions 280 and 290. The sidewall spacers include gate sidewall spacers291 and 292 formed on opposite sides of the gate 220. These sidewallspacers may be the same as the sidewall spacers discussed above forpreventing the source/drain contacts 212 and 225 from shorting to thegate 220. The sidewall spacers also include sidewall spacers 293 and 294positioned at opposite ends of the fins, as shown in FIG. 2E. Each ofthese sidewall spacers 293 and 294 may be formed on a sidewall of arespective dummy poly structure (not shown). The sidewall spacers291-294 are formed before the epitaxial growth that forms the mergedportions 280 and 290. During epitaxial growth, the sidewall spacers291-294 help confine the epitaxial growth within the desired boundariesfor the merged portions 280 and 290. It is to be appreciated thatembodiments of the present disclosure are not limited to this example,and that the merged portions 280 and 290 may be formed using otherfabrication techniques. Also, it is to be appreciated that the sidewallspacers may extend further in lateral direction 122 than shown in FIG.2E.

A multi-finger transistor includes multiple gates arranged in parallel,in which each gate is referred to as a finger. The multi-finger may bemodeled as multiple transistors coupled in parallel, in which each gate(finger) corresponds to one of the transistors. Multi-finger transistorsare commonly used for I/O drivers and/or other types of circuits.

The parasitic resistance of a multi-finger transistor can be reduced byadding more fingers to the multi-finger transistor. However, this cansubstantially increase power consumption and area of the multi-fingertransistor. Aspects of the present disclosure are able to reduceparasitic resistance of a multi-finger transistor without having to addmore fingers to the multi-finger transistor, as discussed further below.

FIG. 3A shows a top view of a two-finger transistor 310 according toaspects of the present disclosure. The two-finger transistor 310includes the fins 210-1 to 210-4 shown in FIGS. 2A-2B, which extend inlateral direction 112. The two-finger transistor 310 also includes thefirst source/drain contact 215, the gate 220, and the secondsource/drain contact 225 shown in FIGS. 2A-2B, which extend in lateraldirection 122. In the discussion below, the gate 220 is referred to asthe first gate 220.

The two-finger transistor 310 also includes a second gate 320 and athird source/drain contact 315. The second gate 320 is formed over aportion of the fins 210-1 to 210-4. The second gate 320 may wrap aroundthree or more sides of each fin (e.g., the top side and two oppositesidewalls of each fin). The second gate 320 runs parallel to the firstgate 220. As shown in FIG. 3A, the second source/drain contact 225 isbetween the first and second gates 220 and 320.

The third source/drain contact 315 is located on the opposite side ofthe second gate 320 as the second source/drain contact 225. The thirdsource/drain contact 315 is formed over a portion of the fins 210-1 to210-4, and may be made of one or more conductive materials (e.g., copperand/or another metal). The third source/drain contact 315 includes afirst extended portion 314 that extends beyond one edge of the activeregion 212, as shown in FIG. 3A. The first extended portion 314 does notoverlap the fins 210-1 to 210-4. As discussed further below, the firstextended portion 314 increases the area of the third source/draincontact 315, allowing more than one VD via to be placed on the thirdsource/drain contact 315 for reduced parasitic resistance. It is to beappreciated that the portions of the fins under the first, second andthird source/drain contacts 215, 225 and 315 may be merged, as discussedabove with reference to FIG. 2D. The portions of the fins under thefirst and second gates 220 and 320 are separate (i.e., not merged).

FIG. 3B shows a top view of the contact interface structures for thetwo-finger transistor 310 up to the M0 layer according to aspects of thepresent disclosure. Note that the individual fins are not shown in FIG.3B for ease of illustration. FIG. 3C shows a perspective view of theinterface structures for the two-finger transistor shown in FIG. 3B.

The contact interface structures for the two-finger transistor includethe first, second, third and fourth M0 lines 235, 236, 255 and 256. Asshown in FIGS. 3B and 3C, the first and second M0 lines 235 and 236extend over the third source/drain contact 315 and the first and secondgates 220 and 320 in direction 112.

The contact interface structure for the first source/drain contact 215includes VD via 232 connecting the first source/drain contact 215 to thefirst M0 line 235, and VD via 231 connecting the first source/draincontact 215 to the second M0 line 236. VD via 232 lies within the activeregion 212, and VD via 231 lies within the first extended portion 214 ofthe first source/drain contact 215. In FIG. 3B, the VD vias are shown indashed lines to indicated that they are under the M0 lines.

The contact interface structure for the third source/drain contact 315includes VD via 332 connecting the third source/drain contact 315 to thefirst M0 line 235, and VD via 331 connecting the third source/draincontact 315 to the second M0 line 236. VD via 332 lies within the activeregion 212, and VD via 331 lies within the first extended portion 314 ofthe third source/drain contact 315. In this example, the first and thirdsource/drain contacts 215 and 315 are shorted together through the firstand second M0 lines 235 and 236. This is because the first M0 line 235is connected to the first and third source/drain contacts 215 and 315 byvias 232 and 332, respectively, and the second M0 line 236 is connectedto the first and third source/drain contacts 215 and 315 by vias 231 and331, respectively.

The contact interface structure for the second source/drain contact 225includes VD via 252 connecting the second source/drain contact 225 tothe third M0 line 255, and VD via 251 connecting the second source/draincontact 225 to the fourth M0 line 256.

As shown in FIG. 3B, the VD vias 232 and 231 of the first source/draincontact 215 are approximately aligned with the VD vias 332 and 331 ofthe third source/drain contact 315 in direction 122, and are offset fromthe VD vias 252 and 251 of the second source/drain contact 315 indirection 122.

The extended portions of the source/drain contacts 215, 225 and 315expand the contact areas of the source/drain contacts 215, 225 and 315,allowing additional VD vias 231, 331 and 252 to be placed on thesource/drain contacts for reduced parasitic resistance, as shown inFIGS. 3B and 3C. Without the extended portions, the interface structureswould be limited to VD vias 232, 332 and 251 within the active region212.

FIG. 4 shows an exemplary circuit model 400 of the two-fingertransistor. In this example, the two-finger transistor is modeled asfirst and second transistors 410 and 420 connected in parallel. Thefirst transistor 410 has a gate corresponding to the first gate 220, adrain corresponding to the first source/drain contact 215, and a sourcecorresponding to the second source/drain contact 225. The secondtransistor 420 has a gate corresponding to the second gate 320, a draincorresponding to the third source/drain contact 315, and a sourcecorresponding to the second source/drain contact 225. In this example,the second source/drain contact 225 is shared by the first and secondtransistors 410 and 420, and therefore the first and second transistors410 and 420 have a common source. Also, the drains of the first andsecond transistors 410 and 420 are connected together at the M0 layerthrough the first and second M0 lines 235 and 236, as discussed above.

FIG. 3D shows a top view of the contact interface structures for thetwo-finger transistor 310 from the M0 layer to the M1 layer according toaspects of the present disclosure. Note that structures below the M0layer are not shown in FIG. 3D for ease of illustration.

The contact interface structures for the two-finger transistor includethe first and second M1 lines 240 and 260 shown in FIG. 2A, and a thirdM1 line 340. The third M1 line 340 may extend in the lateral direction122 above the third source/drain contact 315 (shown in FIGS. 3B and 3C).In FIG. 3D, structures below the M1 lines are shown in dashed lines. Theboundary of the active region 212 is also shown using dashed lines.

The contact interface structures also include V0 via 238 connecting thefirst M0 line 235 to the first M1 line 240, and V0 via 237 connectingthe second M0 line 236 to the first M1 line 240. The contact interfacestructures may also include V0 via 338 connecting the first M0 line 235to the third M1 line 340, and V0 via 337 connecting the second M0 line236 to the third M1 line 340. The contact interface structures mayfurther include V0 via 258 connecting the third M0 line 255 to thesecond M1 line 260, and V0 via 257 connecting the fourth M0 line 256 tothe second M1 line 260.

Note that the interface structures for the gates 220 and 320 are notshown in FIGS. 3B-3D. The interface structure for the first gate 220 maybe the same as the gate interface structure for the first gate 220 shownin FIG. 2A. The interface structure for the second gate 320 may be aduplicate of the interface structure for the first gate 220. In thisexample, the fifth M0 line 245 may extend to the second gate 320 suchthat the first gate 220 and the second gate 320 are connected throughthe fifth M0 line 245.

It is to be appreciated that the M0 and M1 layers discussed above arenot limited to the terms “M0” and “M1.” For example, if the bottom-mostinterconnect metal layer starts with a metal-layer index of one insteadof zero, then the M0 and M1 layers may be referred to as the M1 and M2layers, respectively.

Within the present disclosure, the word “exemplary” is used to mean“serving as an example, instance, or illustration.” Any implementationor aspect described herein as “exemplary” is not necessarily to beconstrued as preferred or advantageous over other aspects of thedisclosure. Likewise, the term “aspects” does not require that allaspects of the disclosure include the discussed feature, advantage ormode of operation.

In this disclosure, the term “connect” means electrically connect, anddoes not exclude the possibility of an intervening conductive element(e.g., thin conductive interface). For example, an element may connectto another element by making direct electrical contact with the otherelement, or through an intervening conductive element.

The previous description of the disclosure is provided to enable anyperson skilled in the art to make or use the disclosure. Variousmodifications to the disclosure will be readily apparent to thoseskilled in the art, and the generic principles defined herein may beapplied to other variations without departing from the spirit or scopeof the disclosure. Thus, the disclosure is not intended to be limited tothe examples described herein but is to be accorded the widest scopeconsistent with the principles and novel features disclosed herein.

1. A die, comprising: one or more fins; a gate formed over a first portion of the one or more fins; a first source/drain contact formed over a second portion of the one or more fins, wherein the first source/drain contact includes an extended portion that does not overlap the one or more fins; first and second metal lines formed from a first metal layer, wherein the first and second metal lines are spaced apart; a first via connecting the first source/drain contact to the first metal line; and a second via connecting the first source/drain contact to the second metal line, wherein the second via lies within the extended portion of the first source/drain contact.
 2. The die of claim 1, wherein the first via overlaps the one or more fins.
 3. The die of claim 1, wherein the one or more fins comprise multiple fins.
 4. The die of claim 3, wherein the multiple fins are merged under the first source/drain contact.
 5. The die of claim 1, further comprising: a third metal line formed from a second metal layer, wherein the second metal layer is above the first metal layer; a third via connecting the first metal line to the third metal line; and a fourth via connecting the second metal line to the third metal line.
 6. The die of claim 5, wherein the third metal line is perpendicular to the first and second metal lines.
 7. The die of claim 5, wherein the third metal line runs parallel with the first source/drain contact.
 8. The die of claim 1, further including: a second source/drain contact formed over a third portion of the one or more fins, wherein the second source/drain contact includes an extended portion that does not overlap the one or more fins; third and fourth metal lines formed from the first metal layer, wherein the third and fourth metal lines are spaced apart; a third via connecting the second source/drain contact to the third metal line, wherein the third via lies within the extended portion of the second source/drain contact; and a fourth via connecting the second source/drain contact to the fourth metal line.
 9. The die of claim 8, wherein the extended portion of the first source/drain contact and the extended portion of the second source/drain contact are located on opposite sides of the one or more fins.
 10. The die of claim 8, wherein each of the first and fourth vias overlaps the one or more fins.
 11. The die of claim 8, wherein the one or more fins comprise multiple fins.
 12. The die of claim 8, wherein the first, second, third and fourth metal lines run parallel with one another.
 13. The die of claim 8, wherein the first source/drain contact and the second source/drain contact are located on opposite sides of the gate.
 14. A die, comprising: one or more fins; a first gate formed over a first portion of the one or more fins; a first source/drain contact formed over a second portion of the one or more fins, wherein the first source/drain contact includes an extended portion that does not overlap the one or more fins; a second source/drain contact formed over a third portion of the one or more fins; a second gate formed over a fourth portion of the one or more fins, wherein the second source/drain contact is between the first gate and the second gate; a third source/drain contact formed over a fifth portion of the one or more fins, wherein the third source/drain contact includes an extended portion that does not overlap the one or more fins; first and second metal lines formed from a first metal layer, wherein the first and second metal lines are spaced apart; a first via connecting the first source/drain contact to the first metal line; a second via connecting the first source/drain contact to the second metal line, wherein the second via lies within the extended portion of the first source/drain contact; a third via connecting the third source/drain contact to the first metal line; and a fourth via connecting the third source/drain contact to the second metal line, wherein the fourth via lies within the extended portion of the third source/drain contact.
 15. The die of claim 14, wherein the each of the first and third vias overlaps the one or more fins.
 16. The die of claim 14, wherein the one or more fins comprise multiple fins.
 17. The die of claim 16, wherein the multiple fins are merged under the first, second and third source/drain contacts.
 18. The die of claim 14, wherein the second source/drain contact has an extended portion that does not overlap the one or more fins, and the die further comprises: third and fourth metal lines formed from the first metal layer, wherein the third and fourth metal lines are spaced apart; a fifth via connecting the second source/drain contact to the third metal line, wherein the fifth via lies within the extended portion of the second source/drain contact; and a sixth via connecting the second source/drain contact to the fourth metal line.
 19. The die of claim 18, wherein the extended portion of the first source/drain contact and the extended portion of the second source/drain contact are located on opposite sides of the one or more fins.
 20. The die of claim 18, wherein the first, second, third and fourth metal lines run parallel with one another. 